SRAM circuit designs are very hard to model accurately because of the small size of the SRAM cell. SRAM performance data, based on traditional modeling and simulation often does not represent the performance of the hardware, it was intended to model and simulate. FET models that are used to model hardware are limited in their application to SRAM cells as these models are based on DC type measurements. These FET models are not accurate in predicting AC Read/Write operations in SRAM memory arrays. There are several reasons for this. SRAM cells are sensitive devices whose performance is greatly affected by process imperfections and process variations. An SRAM cell has unique properties, layout, and often sub-minimum device geometry as compared with other FET integrated circuits. Due to its small device widths, the SRAM is sensitive to process parameter variations, and in addition does not scale well with changes in technology.
Prior art model to hardware correlation for SRAM cells is carried out with SRAM array peripheral circuits in SRAM macros, thereby exercising read, write, and other functional modes of operation. Hence the characterization of the SRAM cell itself is often limited to the accuracy of the peripheral circuits. The prior art does not directly measure SRAM cell AC characteristics from hardware.